1. Field of the Invention
The present invention relates to an integrated circuit (IC) that implements the JTAG test port while providing for the high-speed testing of a programmable digital processor.
2. Description of the Prior Art
The development of complex integrated circuits increasingly depends upon the ability to test the circuitry sufficiently to ensure proper operation. This is increasingly difficult as the number of logic gates in a given integrated circuit increases. The input test data (referred to as "vectors") must also increase, so that all possible input states, or at least a significant portion of them, are included in the test program. Traditionally. digital processors have been tested for functionality in the factory on a commercial test machine. Either the wafer is probed or the packaged part is tested. A sequence of vectors is applied in parallel to the input pads or pins and comparisons with expected results are performed on output pads or pins. The fault coverage is usually less than 100% and is dependent on how many vectors there are, how well the vectors were written, and the degree of complexity of the circuitry to be tested.
The problems with this prior-art testing scheme include the fact that commercial test sets are having difficulty working fast enough to test very fast parts. The only way to test the packages once they have been soldered into boards is to come down with a custom "bed of nails" that disables other chips on the board and applies vectors to the package under test. This is increasingly difficult as the industry goes to surface mount packages on both sides of a printed circuit board. It is not possible to test the package in the field or even in the factory when the printed circuit board is plugged in to its slot. In an application specific integrated circuit (ASIC) methodology, a core processor can end up embedded in a design such that the standard vector set of tests cannot be applied from the bond pads.
Many have advocated dealing with the test problems by adding Built In Self Test (BIST) circuitry to a chip. Here, a signal applied to the chip causes the BIST circuitry to perform a test. Typically, there is a pseudo-random sequence produced by a shift register with feedback. The sequence is applied to circuitry under test and the outputs from the circuitry are compressed and compared with an expected signature. BIST has been used successfully in a number of chips. The problems with this testing scheme include: While BIST solutions are known for regular structures such as memories, there is no general way known to produce BIST for arbitrary random logic with arbitrarily high fault coverage. Also, there can be a problem with BIST with an error condition aliasing to the same signature as a passing condition. In addition, BIST requires adding area overhead and possibly speed overhead to the chip.
A recent development in integrated circuit testing is the use of the so-called JTAG (i.e., Joint Test Action Group) test port for in situ testing of IC chips mounted on a board. This standard has been adopted by the Institute of Electrical and Electronics Engineers, Inc., and is now defined as the IEEE Standard 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture, which is incorporated herein by reference. An overview of the development, definition, and application of this standard is provided in The Test Access Port and Boundary-Scan Architecture, C. M. Maunder and R. E. Tulloss, published by the IEEE Computer Society Press, Los Alamitos, Calif. (1990). Referring to FIG. 3, in the JTAG scheme, a four (or optionally five) signal Test Access Port (TAP) is added to each chip or grouping of chips on a board. The TAP includes three inputs: a test clock (TCK), a test mode select (TMS), and test data in (TDI). In addition, there is one output, test data output (TDO). TDI and TDO are daisy-chained from chip to chip, whereas TCK and TMS are broadcast.
Every JTAG chip contains a boundary scan register (300), and a bypass register (301). The boundary scan register provides for serially shifting any desired data pattern from the TDI port into the input stages of the chip. The boundary scan register also provides for receiving the output data of each output stage of the chip, and for serially shifting these bits out through the TDO port. Inputs from the chip terminals I.sub.1 . . . I.sub.3, and system clock terminal CKI are provided to the boundary scan register. These may be output from the boundary scan register to the chip circuitry by lines JI.sub.1 . . . JI.sub.3, and JCKI, respectively. (Other lines, not shown, are used to send signals in the other direction, from the chip output circuitry to the chip output terminals.) Each chip also contains a TAP controller (302) that implements a standard state machine steered by the TMS signal. In this regard, the TAP controller selects one of sixteen states for shifting data and instructions into the registers, among other functions. The instruction register (303) allows test instructions to be entered into each chip, and the instruction decoder (304) serves to decode the instructions. Extra "Status" data bits may defined by the user for inclusion in the instruction register, in addition to mandatory instruction bits. The output of a given register is selected by multiplexers 307 and 308, and driven off-chip by the output buffer (309), which supplies the TDO signal. The external signals applied to the JTAG test access port are provided by a master controller, also referred to as the "JTAG master" herein.
The JTAG standard allows a chip to have arbitrary data serially scanned into its boundary scan register (300), with each bit position corresponding to an input or output terminal of the chip. The data may then be applied as if it were test vector input to the chip or output from the chip. The JTAG standard also supports tri-stating outputs. A standard scheme allows opens and shorts on the board or bond wires to be located. A chip can be tested by applying its entire factory vector set in serially through the boundary scan register. The JTAG standard also allows for optional registers to be added. For example, a manufacturer's identification register (305) provides a unique code identifying the chip type. In addition, a user test register (306) may be defined, typically to provide support for triggering BIST and reading the test status results. However, a problem with the JTAG testing scheme as it has been developed to this point is that testing of a chip by serial scanning is very slow; hence functional testing cannot be performed at full chip speed.